The present invention relates generally to semiconductor processing, and more particularly to structures and methods for planarization of dielectric layers around metal patterns for optical efficiency enhancement.
The development and deployment of optical devices such as CMOS image sensor and charge-coupled devices (CCD) have been growing rapidly in recent years. These devices have many special requirement compared to general logic device. For example, one of the requirements is the reduction of thickness of optical transparent dielectric in a backend passivation layer such as silicon oxide, silicon nitride or silicon oxynitride. Another requirement is the uniform thickness of the optically transparent dielectric material in the regions between metal patterns, as well as the uniform thickness of the dielectric material over the patterned metal. The metal pattern is used to block electromagnetic radiation, especially light, in the optical wavelength range. The incident light will pass through locations between metal patterns to an optical sensing unit formed in or on the substrate. The non-uniform thickness of optical transparent dielectric in the areas between metal patterns will change the refractive index which results in discolor phenomenon.
Due to the loading effect of chemical mechanical polishing (CMP), the dielectric between adjacent metal patterns may not be planar; rather, the dielectric may include a slanted or inclined surface. The slanted or incline surface of dielectric is indicative of thickness non-uniformity, which not only causes visual discolor but also degrades a sensor's performance.
Therefore, desirable in the art of semiconductor processing are methods to improve planarization of dielectric layers for better optical efficiency.